In EEPROM memories, the logic value of a bit stored in a memory cell is represented by the value of the threshold voltage of a floating-gate transistor, which can be modified at will by erasing or programming operations. The programming or erasing of a floating-gate transistor includes injecting electrical charges into the gate of a transistor, or extracting electrical charges therefrom, through the tunnel or Fowler-Nordheim effect via a programming/erase voltage Vpp that may be around 10 to 20 volts.
To read such a memory cell, the threshold voltage of the transistor is compared with a reference voltage which, in general, is substantially midway between the negative threshold voltage of a programmed transistor and the positive threshold voltage of an erased transistor. In practice, this comparison is made by applying a read voltage substantially equal to the reference voltage on the gate of the transistor and then observing whether the transistor is in the on-state or the off-state. The on-state or off-state of the transistor is detected by a read circuit commonly referred to by those skilled in the art as a “sense amplifier” connected to the bit line to which the floating-gate transistor is itself connected. During this read process, an erased transistor remains in the off-state since its threshold voltage is above the read voltage. In this way, no current can flow in the bit line and this corresponds to a first logic state of the bit stored in the cell, for example a bit of logic value zero.
A programmed transistor is, on the contrary, in the on-state since its threshold voltage is below the read voltage. In this case, a current flows in the bit line and this corresponds by convention to a bit having the opposite logic value, for example the logic value 1. Conventional architectures of EEPROM memory cell units are illustrated in FIGS. 1 and 2. More precisely, in FIG. 1, the memory cell unit MCU is made up of a memory cell CEL comprising a transistor FGT having a control gate CG and a floating gate FG. The cell CEL is connected to a bit line BL via a bit line select transistor BLST.
The cell also includes a control gate select transistor CGST connected between a gate control line GCL and the control gate CG of the floating-gate transistor FGT. The gates of the transistors COST and BLST are connected to a word line WL conventionally extending perpendicular to the bit line BL. The architecture in FIG. 1 therefore provides one memory cell per bit. To erase the cell, the programming voltage Vpp is applied on the word line WL and on the gate control line GCL, whereas a zero voltage is applied on the terminal GND connected to the source of the transistor FGT, the bit line BL generally being left floating.
In writing, the programming voltage is applied on the word line WL while a zero voltage is applied on the line GCL. To write a “1” (for example), the programming voltage Vpp is applied on the bit line BL, whereas this bit line BL is left floating to write a “0”. In both cases, the terminal GND is floating.
In general, words of x bits, typically 8 bits, forming in this case eight-bit bytes, are stored in the EEPROM memory. Typically, the storage zone of an eight-bit byte therefore comprises eight memory cell units plus one control gate select transistor CGST (since in general the control gates of the eight memory cells of the eight memory cell units are all connected together and selected from the line GCL) and a ground line. Programming an eight-bit byte is therefore made up of an overall word erase cycle followed by a selective write cycle.
To improve the reliability of memory cell units, it is possible to use architectures having two cells per logic bit, as illustrated in FIG. 2. The logic state “1” or “0” of a bit, or logic bit, is then represented by two data bits. The purpose of such architectures is to maintain data integrity if one of the paired memory cells is out of action. With such architectures, it is possible to store a binary data bit twice or else, as illustrated in FIG. 2, one binary data bit in one of the memory cells and the complementary binary data bit in the other memory cell.
More precisely, a memory plane MP having two cells per bit comprises in this case two memory cells CEL1 and CEL2 each having a bit line select transistor BLST1, BLST2 and a floating-gate transistor FGT1, FGT2. A single control gate select transistor CGST is provided for controlling the two control gates CG1, CG2 of the transistors FGT1, FGT2. With such an architecture, an eight-bit byte therefore typically comprises 16 memory cells plus one control gate select transistor CGST.
To be able to program more rapidly, for example, to reduce the programming time by a factor of two, it is possible to provide an individual control gate select transistor per memory cell, so that each memory cell can be individually erased. Thus, it is possible to simultaneously erase certain cells and to write others. With such an architecture, an eight-bit byte therefore comprises 16 memory cells and 16 control gate select transistors. Moreover, each memory cell must have a dedicated ground line, which results in a total of 16 ground lines.
Another approach, enabling two cells per bit to be combined and with simultaneous electrical erasing, could include, in the case of an eight-bit byte, reproducing the architecture of FIG. 2 eight times, which therefore results in 16 memory cells, 8 control gate select transistors and 8 ground lines, since one ground line is dedicated per pair of cells. Thus, whatever the option chosen, storing a digital word with two cells per bit, while being able to erase and write simultaneously, is costly in terms of area.